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Part Number: LMKDB1108 Other Parts Discussed in Thread: LMK1C1108 , Tool/software: Dear TI,
looking at the jitter specifications reported in the datasheet , the LMK1C1108 has better jitter specification than LMKDB1108 (LMK1C1108: 20fs max/8fs typ @ 156M…
Part Number: LMKDB1108 Tool/software: I am not able to get LOS# to go low when the clock is removed from the input.
1) Are there any register bits that can mask an LOS# event?
2) Is there anything that can disable the LOS# function…
Part Number: LMKDB1108 Tool/software: Hi TI Team,
I would like to use LMKDB1108 because of it's low jitter for non-PCIE (156.25MHz) applications. My receiver is CML instead of LP-HCSL. How would i implement the translation from LP-HCSL to CML or if…
Hi Kevin,
Thank you for your patience. I took our EVM into the lab and tried to simulate your issue by holding the CLKIN pins around 750mV. When I did this, the device did not recognize this as a valid input, and the LOS# pin stayed low.
I have a few…
Part Number: LMKDB1108 Tool/software: I would like to use the LMKDB1108 as a clock buffer in a non-PCIe application due to its very low power. I have couple questions: 1) Can the LMKDB1108 be driven single-ended from a LVCMOS 3.3V source with a resistive…
Part Number: LMKDB1108 Tool/software: Hi team,
I would like to ask about the lmkdb1108 clock buffer. When used in PCIe 5.0 scenarios, the datasheet states that the jitter typical value is <5fs.
I would like to ask about the jitter value. Does the…
Part Number: LMKDB1108 Other Parts Discussed in Thread: LMKDB1102 , CDCE6214-Q1 , , LMK3H0102 Hi Sirs
I am finding a clock generator which's behavior like LMK1102 for PCIE application。
Our processor have one pair differential clock output, and plan to…
Part Number: LMKDB1108 Hello team,
On the datasheet, the input clock slew rate is minimum 0.6V/ns when differential clock. Would it be same for single ended clock, if the amplitude is 300mVpp?
Best Regards, Kei Kuwahara
